A well recognized problem in the testing of logic circuits embedded on integrated circuit chips is that of the unavailability of the circuit input and output connections. This unavailability is due to the limited number of input/output (I/O) pins available on the chip package. To test these embedded circuits, various means such as level sensitive scan design (LSSD) shift registers have been developed for applying test data and reading test results through a limited number of I/O pins. Assuming that the correct types of test data are applied through these means, many types of logic circuit faults become readily detectable. Stuck-at-level faults, for example, wherein the output of a logic circuit is stuck at a logical level, are typically readily detectable through the LSSD shift registers.
Other types of logical circuit faults are not readily detectable solely through the use of the above described test means, and require the co-location of dedicated test circuitry with the logic circuits to be tested. U.S. Pat. No. 4,410,816 to Kanai, for example, shows an emitter-coupled-logic (ECL) circuit wherein a test circuit is provided for aiding in the detection of open circuit faults at the emitter of an emitter-follower output stage.
One type of logic fault which has not been adequately addressed by the prior art is that known as a "stuck-near-threshold" fault. When a stuck-near-threshold fault occurs, the output of a logic element becomes stuck near the threshold differentiating its high and low logical states. As described above, the output of a logic circuit exhibiting such an error must at least be registered, and often propagated through subsequent logical circuit stages, before being available at a chip output. Because the logic circuit output is stuck close to the logical threshold, it may be registered, or detected at subsequent stages, at varying times as either a logical high, or a logical low. This makes reliable and repeatable detection of the stuck-near-threshold fault very difficult.
The present invention is directed to the detection of such stuck-near-threshold faults in differential current switching (DCS) logic elements. It has particular application to such DCS elements embedded on integrated circuit chips.
U.S. Pat. No. 4,656,417, to Kirkpatrick et al., (assigned to the assignee of the present invention) shows a test circuit for detecting stuck-near-threshold faults in a differential cascode voltage switch. The circuit in Kirkpatrick et al. tests for two invalid states (0,0 and 1,1), and holds the fault in a latch. The Kirkpatrick et al. circuit, however, does not show or suggest a means for detecting such faults in a DCS circuit.
Referring now to FIG. 1, a conventional DCS logic circuit 10 is shown including a differential current switch 11, responsive to input signals applied on terminals 12a, 12b, for steering a current I1 selectively through a resistor R1 or a resistor R2. DCS 11 comprises, for example, an emitter-coupled logic (ECL) arrangement of bipolar transistors, many configurations of which are well known to those skilled in the art. A bias potential V.sub.CC is applied to DCS 11 through resistors R1, R2. In operation, as current I1 is directed selectively through resistor R1 or R2, the voltage signals at circuit nodes A, B between resistors R1, R2 and DCS 11 change levels relative to one another. The relative polarities of the signals at circuit nodes A, B indicate a logical low/0 or a logical high/1 signal to a subsequent logic circuit (not shown).
Referring now to FIG. 2, a graph 14 is shown illustrating a proper logical output for circuit 10. Graph 14 shows the signals at nodes A, B plotted against a vertical axis V representing voltage and a horizontal axis T representing time. Reference levels on voltage axis V are indicated at HI, TH(reshold), and LO. In accordance with a proper logical output for a DCS circuit, the HI voltage level at node A is above threshold voltage level TH, the LO voltage level at node B is below the threshold voltage level, and the difference voltage V.sub.D between the voltage levels at nodes A and B is greater than a stuck-near-threshold voltage range V.sub.SNT. Stuck-near-threshold voltage range V.sub.SNT is centered about the threshold voltage level TH, and comprises a selected voltage range, for example 0.15 volts for bipolar logic, below which noise prevents a correct determination of the logic signal with acceptable accuracy. With the relative signal levels A&gt;B defined as a logical 1, and B&gt;A defined as a logical 0, circuit 10 is thus outputting a valid logical 1. It will be understood that the voltages HI, Th, and LO are relative as described above, and that threshold voltage level TH needn't be centered between the bounding two. It will be further understood that, if circuit 10 were operated to provide a logical output of 0, the signals at nodes A, B would reverse polarity with respect to threshold level TH, and again differ by at least stuck-near-threshold voltage range V.sub.SNT.
FIG. 3 comprises a plot 16 identical to plot 14 excepting that it illustrates the signals present at nodes A, B when circuit 10 exhibits a stuck-near-threshold fault. As shown, the signals at nodes A, B are stuck near the HI voltage, and, more importantly, do not differ from each other by at least stuck-near-threshold voltage range V.sub.SNT. It will be understood that the stuck-near-threshold fault is characterized by the relative difference between the output voltages being less than the stuck-near-threshold voltage range V.sub.SNT, regardless of the voltage levels at which the output voltages are stuck.
Referring now to FIG. 4, a prior art circuit 10' is shown which operates to help in identifying stuck-near-threshold faults in DCS logic circuits. Circuit 10' is identical in construction to circuit 10 of FIG. 1 above, with the exception of the application of a separate bias potential V'.sub.CC to resistor R2. Identical elements between FIGS. 1 and 4 are indicated with like reference numbers. Bias potentials V'.sub.CC, and V.sub.CC are selected such that, when no current is steered through resistors R1 or R2, the inherent potential difference between circuit nodes A, B is greater than the threshold voltage for circuit 10'.
In normal operation, the steering of current I1 through resistors R1 or R2 establishes output signals at nodes A, B exhibiting a potential difference sufficient to overcome the above-described inherent potential difference, thereby providing a valid logical signal output. When, however, there is a fault in circuit 10' such that the output signals on circuit nodes A, B would otherwise exhibit a stuck-near-threshold fault, the inherent potential difference established between bias potentials V.sub.CC and V'.sub.CC across resistors R1, R2 is sufficient to pull the output signals to predetermined levels, establishing what appears to be a stuck-at-level (i.e. stuck-at-zero or stuck-at-one) fault. As described above, these stuck-at-zero and stuck-at-one faults are detectable through the application of appropriate test data. While the exact nature of the circuit fault (i.e. stuck-near-threshold) may not be known, the circuit is never the less identified as bad.
While circuit 10' includes features which function to help identify stuck-at-threshold faults in differential current switching logic circuits, these features cause circuits incorporating them to exhibit significant operational disadvantages. More specifically, circuits employing the voltage divider and inherent potential difference of circuit 10' above exhibit reduced noise margins, and require a relatively large signal swing to overcome the inherent potential difference. This large signal swing requires significant circuit delays, making circuit 10' substantially slower in operation than circuit 10 (FIG. 1). Additionally, the requirement to supply second bias potential V'.sub.CC to each DCS circuit significantly increases the overhead and hence cost of an integrated circuit chip.